Conventionally, technology that simulates the functions and performance of central processing units (CPUs) has been disclosed. For example, technology exists that converts program code so that operations can be executed at a host CPU that executes simulations for a target CPU subject to evaluation, thereby simulating the functions, performance, and power consumption of the target CPU.
For example, technology exists where before simulation, the code of the target CPU is converted into host code that enables direct execution thereof in units of subroutines by a host computer and registers that are used between the in and the out of blocks, which are obtained by separating the code into units of subroutines, are analyzed. See, for example, Japanese Laid-Open Patent Publication No. H9-6646.
Nonetheless, with the conventional technologies above, since simulation is executed for each block, if simulation is executed for multiple blocks successively, the simulation results are inaccurate and deviate from actual execution results.